1. Technical Field
The present invention relates in general to bus driver circuits in data processing systems and in particular to bus driver circuits providing overvoltage protection. Still more particularly, the present invention relates to utilization of stacked PFETs at the output of a bus driver to provide a margin of overvoltage protection under the threshold voltage of an overvoltage device.
2. Description of the Related Art
Contemporary processors typically contain a large number of devices at a high density, forcing the device dimensions to the smallest possible levels. As processor technology advances, device geometries shrink, including gate oxide thicknesses. Reduction of gate oxide thickness, however, is generally attended by a corresponding reduction in the maximum allowable voltage between the device gate and source (V.sub.gs). Excess voltages may damage the gate oxide, precluding the device from proper operation and potentially rendering the processor worthless.
In most data processing system architectures, processors are required to directly interface with a bus connected to various input/output devices such as caches and/or system memories, graphics adapters, bus bridges, etc. Thus processors typically include off-chip drivers for driving the bus conductors of a bus connecting the processor to various other devices. However, processor technology is advancing at a much faster pace than input/output interface voltages. The 5 V or 3.3 V signal voltage levels employed according to most bus specifications, for example, may exceed the maximum allowable voltages for devices within the off-chip driver portion of a processor.
Even where devices within an off-chip driver are designed to tolerate specified signal voltage levels, signal reflections on the bus conductors connected to an off-chip driver may cause high overshoots (voltages in excess of the power supply voltage) and undershoots (voltages below ground or the negative power supply voltage, also called "negative overshoots"). Additionally, off-chip drivers interface with a wide array of devices, such as ASICs and SRAMs, which may individually cause large overshoots or undershoots when driving the system bus. The magnitude of these overshoots and undershoots may easily violate the maximum allowable gate to source/drain voltages allowed by the processor technology. Violation of the maximum V.sub.gs specification may destroy the devices in the off-chip driver.
The potential for violating maximum allowable voltages and thereby damaging devices dictates the need for overvoltage protection circuitry within the off-chip driver. As device geometries shrink, even within the off-chip driver portion of the processor, overshoots and undershoots below the threshold voltage of conventional overvoltage protection circuits may potentially damage devices within the off-chip driver, or at least alter the performance of such devices.
It would be desirable, therefore, to provide overvoltage protection within an off-chip driver which protects even against overshoots and undershoots below the threshold voltage of conventional overvoltage protection circuits.